1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to an input circuit provided in a semiconductor integrated circuit, used in a high-speed small-amplitude signal transmission system for transmitting a high-speed small-amplitude signal through a signal transmission line on a printed circuit board.
2. Description of Related Art
A digital computer includes a plurality of VLSI circuits, which are bi-directionally coupled with a binary communication network through a transmission line of a single segment or a multi-segment. Generally, the transmission line is constituted of a track which is formed on a printed circuit board and which has an input/output interface provided at each of opposite ends thereof. On the other hand, conventional VLSI circuits are formed by a CMOS technology. However, in an input/output interface of a conventional TTL level, if the frequency of the transfer data exceeds 50 MHz. the influence of signal reflections and crosstalk becomes large, with the result that waveform distortion occurs because of ringing and other factors and normal data transfer becomes difficult.
Under this circumstance, other input/output interfaces such as a small amplitude CTT (Center Tapped Termination) and GTL (Gunning Transceiver Logic) in which a signal level on the transmission line is suppressed to 1 V or less have been proposed. In these CTT and GTL, a wiring conductor is terminated at a voltage lower than a power supply voltage, and a driving current of an output circuit is caused to flow through a terminating resistor, so that a signal amplitude of not greater than 1 V is generated across the terminating resistor. With this arrangement, signal reflection is prevented by matching the value of the terminating resistor with a characteristic impedance of the wiring conductor, so that high speed data transmission can be realized. For example, in the GTL rule, an output circuit is formed in the form of an open drain type driver and is matching-terminated, and a terminating voltage V.sub.TT =1.2 V.+-.5%, V.sub.REF =0.8 V, an output high level V.sub.OH =0.8 V+400 mV, an output low level V.sub.OL =0.8 V-400 mV, an input high level V.sub.IH =0.8 V+50 mV, an input low level V.sub.IL =0.8 V-50 mV.
One example of an input circuit included in a semiconductor integrated circuit and used for a high-speed small-signal transmission system is proposed by Japanese Patent Application Pre-examination Publication No. JP-A-07-153908 and European Patent Publication EP-A-0 655 839 (the content of which is incorporated by reference in its entirety into this application) claiming the Convention Priorities based on Japanese patent application for JP-A-07-153908 and two other Japanese patent applications.
Referring to FIG. 1, there is shown a circuit diagram of the prior art input circuit shown in JP-A-07-153908. This prior art input circuit includes an nMOS transistor 101 having a source connected to a transmission signal input terminal 103, a gate connected to an internal reference potential terminal 104 and a drain connected to a node 5, a pMOS transistor 100 having a source connected to a power supply voltage V.sub.CC. a gate connected to ground V.sub.SS, and a drain connected to the node 5, and a waveform shaping inverter 102 having an input connected to the node 5 and an output connected to an output terminal 105. The pMOS transistor 100 is provided as a resistor element. This input circuit is characterized in that it can amplify a small-voltage, small-amplitude signal up to high frequencies.
The internal reference potential is generated by an internal reference potential generating circuit 60 as shown in FIG. 2. This internal reference potential generating circuit 60 includes an nMOS transistor 31 having a source connected to a reference voltage input terminal 34, and a gate connected to a drain thereof, a pMOS transistor 30 having a gate connected to the ground V.sub.SS, a source connected to the power supply voltage V.sub.CC, and a drain connected to the drain of the transistor 31 and an internal reference potential terminal 35, and a capacitor 33 connected between the drain of the transistor 31 and the reference voltage input terminal 34. Thus, a drain voltage of the transistor 31 is outputted as an internal reference potential V.sub.RT from the internal reference potential terminal 35.
Now, an operation of this prior art example will be described with reference to FIGS. 3A, 3B and 3C. FIG. 3A illustrates the input voltage V.sub.IN on the transmission signal input terminal 103, and FIG. 3B illustrates the voltage V.sub.5 on the node 5. FIG. 3C illustrates the input current I.sub.IN flowing through the transmission signal input terminal 103. Here, assume that the power supply voltage V.sub.CC =3.3 V, the ground voltage V.sub.SS =0 V, the reference voltage V.sub.REF =0.8 V, the input high level V.sub.IH /the input low level V.sub.IL =1.2 V/0.4 V, the threshold of pMOS transistor=-0.8 V, and the threshold of nMOS transistor=0.8 V.
In this condition, when the transmission signal V.sub.IN is equal to the reference voltage V.sub.REF, the potential V.sub.5 on the node 5 becomes equal to the internal reference voltage V.sub.RT, as will be understood from a symmetrical circuit construction between the circuits shown in FIGS. 1 and 2. If the transmission signal V.sub.IN becomes higher than the reference voltage V.sub.REF, a gate-source voltage of the nMOS transistor 101 becomes small, and an internal resistance of the nMOS transistor 101 becomes large. Therefore, a drain current of the nMOS transistor 101 becomes small, with the result that a drain voltage of the nMOS transistor 101 elevates, so that the potential V.sub.5 of the node 5 finally becomes equal to the power supply voltage V.sub.CC. To the contrary, if the transmission signal V.sub.IN becomes lower than the reference voltage V.sub.REF, the potential V.sub.5 of the node 5 finally becomes about 0.6 V which is near to the voltage V.sub.IN of the transmission signal. The inverter 102 receives the potential V.sub.5 of the node 5, to shape the transmission signal varying between 0.6 V and 3.3 V to an output signal fully swinging between 3.3 V and 0 V.
As seen from FIGS. 3A, 3B and 3C, when the transmission signal V.sub.IN is at a low level, the input current I.sub.IN constantly flows through the input terminal 103 (here, for convention of explanation, a direction of a current flowing outward from the input terminal is assumed to be a positive direction in FIG. 3C). The reason for this is that since the pMOS transistor 100 is provided as the resistor element in this prior art input circuit, the pMOS transistor is constantly in an ON condition. Therefore, the prior art input circuit disadvantageously consumed a large amount of electric power. This steady current can be reduced by narrowing a gate width of the pMOS transistor or by elongating a gate length of the pMOS transistor. Simultaneously, however, a delay time inevitably increases.
Furthermore, when the transmission signal V.sub.IN is at a low level, since the pMOS transistor is in the ON condition, the potential V.sub.5 of the node 5 becomes higher than the input low level V.sub.IL (0.4 V). According to simulation, the node 5 potential V.sub.5 =0.6 V, which is higher than the transmission signal V.sub.IN =0.4 V, by 0.2 V. Therefore, an operation margin of the inverter 102 is reduced, with the result that an erroneous operation is easy to occur due to noise. If the inverter 102 is improved to prevent this problem, a complicated circuit construction is required, which causes various problems including an increased circuit area, an increased delay time and an increased consumed electric power.
Alternatively, in order to prevent the above mentioned potential elevation, it may be considered to make a driving capacity of the nMOS transistor 101 larger than that of the pMOS transistor 100, for example by increasing the gate width of the nMOS transistor 101 or by narrowing the gate width of the pMOS transistor 100 or elongating the gate length of the pMOS transistor 100. However, this causes various inconvenient problems including an increased circuit area, an increased delay time and an increased consumed electric power.